Where dynamic power goes inside a digital IC

What dynamic power is

A digital IC burns power in two broad ways. Static power is leakage: current that flows even when nothing switches. Dynamic power is the cost of switching: every time a gate output changes state, it charges or discharges a load capacitance.

The textbook estimate is activity factor times capacitance times supply voltage squared times clock frequency. Each term is a lever. You cut activity with clock gating. You cut capacitance with layout. You cut voltage with lower-supply design. Frequency is usually set by the product, so it is the hardest one to touch.

A fourth source sits beside those. Switching happens in bursts, and the supply network that feeds the burst has resistance and inductance. Current that rushes in and rushes back through that network is not doing useful work.

Where the current actually flows

Power enters the die through bondpads, spreads across a metal grid, and reaches the gates through local rails. Ground returns by the same path in reverse. When a block of logic switches together, it pulls a sharp current pulse from the grid and pushes a return pulse into the ground network.

• Power and ground bondpads set the first bottleneck. Their count, placement and inductance matter.
• The on-die grid adds resistance and a little inductance between pad and logic.
• On-die decoupling capacitance supplies the fastest part of each pulse locally.
• Package inductance sits outside the die and sets how quickly off-chip current can respond.

Designers add decoupling capacitance to smooth these pulses. That works, but capacitance costs area, and area costs money. It also does not remove the pulse. It only moves where the pulse is absorbed.

How Current RF approaches it

Current RF's stated premise is that the current pulses in digital circuits carry recoverable energy. According to the company, its CC-100 harvests impulse current that would otherwise be thrown away, inverts it, and feeds a portion back to cancel part of the original pulse. The company has packaged that idea as IP for chip designers.

• CurrentRF PowerPad: dynamic power reduction IP that replaces the power and ground bondpads, with near-zero area increase per the company.
• CurrentRF PowerGrid: a digital power-grid overlay with capacitance multiplication, series inductance nullification, EMI reduction and energy harvesting.
• CC-100IP: the base IP block. CC-100IP-RF adds on-chip RF and EMI reduction, CC-100IP-PI is an adjustable-impedance Hypercapacitor, and CC-100IP-MB is the Mileage Booster version.

The words matter here. Current RF describes PowerPad as a modification of the pads you already need, not a new block you place beside them. For a designer, that is the attractive part: if the claim holds, the footprint stays about the same.

What the numbers say, and who says them

Current RF reports that its IP can reduce digital dynamic currents by up to 40%. For autonomous-EV ICs, the company's technical paper cites 20% to 40% switching and dynamic power reduction using PowerGrid or a ground PowerPad modification. The PowerPad datasheet reports a 25% reduction in effective series inductance (ESL). For the CC-100IP-RF, Current RF reports up to a 600X improvement in reservoir capacitance.

These are company-reported figures. The Current RF site names no independent lab or customer verification. Read each number as a claim tied to a test condition, and ask for that condition. Reservoir capacitance and ESL are circuit quantities you can check on an extracted netlist. Dynamic current reduction depends on workload, so it needs a real activity profile to mean anything.

How to check it in your own flow

Start with the baseline you already trust. Run your power analysis on the existing design with a realistic vector set, not a synthetic toggle rate. Record average and peak supply current, supply droop at the worst block, and simulated ground bounce.

• Get the IP's characterized pad or grid model from Current RF, along with its test conditions.
• Swap it into the same netlist, with the same vectors, voltage and temperature corners.
• Compare average current, peak current, droop and bounce side by side.
• Check the area change against the claim, in your own floorplan.
• Check the EMI side separately, since pulse shape drives it.

Current RF says it will power-analyze your ICs and systems, and design or retrofit its IP into your devices. That service is useful if your team has no spare cycles for the evaluation. Ask what the analysis includes and which of your corners it covers.

Questions to ask before a tape-out

Ask which process nodes the IP has been characterized on. Current RF states that its CC-100 IC is produced on the GlobalFoundries CM018RF process, so check how that maps to your node. Ask whether the IP needs a change to your pad ring rules, and whether your foundry's design rules accept it. Ask what verification collateral ships with it.

The PowerPad, PowerGrid and CC-100IP datasheets are on the Datasheets page, and the family overview is on the Integrated Circuits page.